The present invention pertains in general to buried channel MOSFETs, and more particularly to buried channel MOSFETs with a short channel length.
In most VLSI CMOS processes, the PMOS devices (of whatever channel length) operate as buried-channel devices. This is due to the difference in work function between the heavily phosphorus-doped polysilicon gate and the channel: as the gate oxide thickness is reduced, this work function difference creates a potential gradient, in the crystalline silicon just below the gate oxide interface, which keeps the channel inversion from extending all the way up to the oxide interface (when the transistor is weakly turned on). (In addition, segregation effects will commonly deplete boron dopants from the top 200 or so Angstroms of the channel.)
This effect, and the resulting problems, have been extensively discussed in the literature (see, for example, the IEDM proceedings of 1985, 1986, and 1987). Various attempts have been made to avoid this buried-channel PMOS operation, e.g. by using P-type polysilicon for the gates of the PMOS devices, and N-type polysilicon for the gates of the NMOS devices. However, all such attempts entail additional process complexity.
Thus, many VLSI CMOS processes are now designed to use buried-channel PMOS devices. However, problems arise with buried-channel devices at small geometries (minimum length close to or less than one micron). For example, such devices tend to have increased susceptibility to punchthrough, since the greater separation between the gate and the channel makes the device more likely to exhibit two-dimensional behavior.
Punchthrough is caused when the electric fields, from the voltage applied on the transistor's drain terminal, extend into the channel region and change the profiles of depletion regions there. If a transistor's channel were infinitely long, the electric fields in the middle of the channel would be controlled entirely by the gate; but, as the drain and the source are brought closer together, the fields from the drain also affect the channel. Thus, in a small-geometry buried-channel PMOS device, the surface depletion region under control of the gate may no longer able to fully pinch off the channel region when the drain has a large voltage potential disposed thereon. These changes may allow holes to flow through the buried channel region, even though the gate voltage would not of itself be sufficient to turn the device on. This is effect allows the drain to "punch through" the buried channel region to connect with the source of the transistor. Even when the transistor is not fully turned on, the electric field contribution of the drain (known as "drain-induced barrier lowering") may cause increased leakage current from source to drain, through the buried channel.
When a MOS transistor receives an applied gate voltage which (for a PMOS device) is greater than its threshold voltage (or, for an NMOS device, is less than the threshold voltage), the transistor will not be fully turned on. However, the transistor will normally conduct a small amount of current ("subthreshold current"), which depends exponentially on the difference between the applied voltage and the threshold voltage. This relation will be dependent on the specific device parameters, but a typical number might be a tenfold current reduction for each 80 milliVolts by which the applied gate voltage exceeds the threshold voltage. In digital circuits this subthreshold current is generally undesirable.
In the fabrication of IGFET (MOS) transistors, techniques of ion implantation into the channel region have been widely utilized, to facilitate processing or to improve the operating parameters of the transistor. For example, channel implants have been utilized to provide threshold voltage adjustment, to reduce punch-through between the source and drain, and for forming a buried-channel device by incorporating within the surface region dopants of the type opposite to that of the substrate dopants.
In the buried channel MOSFET, the conducting channel is in the bulk semiconductor rather than at the Si--SiO.sub.2 interface as in a conventional MOSFET. The actual doping profile for the channel region typically has the peak centered in the channel region. Therefore, a surface depletion region is formed at the Si--SiO.sub.2 interface, and a junction depletion region is formed about the metallurgical junction (beneath the surface of the substrate). The width of these two depletion regions depends upon the applied voltages. The gate of the transistor modulates the width of the surface depletion region.
A buried channel MOSFET can be fabricated as a normally-on or a normally-off device, depending on the surface doping and junction depth. In a normally-off device, the junction depletion region and the surface depletion region normally touch or overlap to pinch off the buried channel region. The voltage difference between the gate, the Fermi level of the channel region and the Fermi level of the underlying substrate are such that the channel region is depleted of carriers. The gate voltage is then operable to vary the surface depletion region to allow, for example, holes in the P-channel transistor to flow from the source to the drain.
As channel lengths decrease further in MOSFETs, other departures from long channel behavior may occur. These departures (known as short channel effects) arise as a result of a two-dimensional distribution of high electric fields in the channel region. One might consider attempting to avoid these short channel effects by simply scaling down all dimensions and voltages of a long channel MOSFET, so that the internal electric fields are the same. Traditionally, such shrinking would include adjustments to oxide thickness, channel length, channel width, and junction depth. In addition, doping levels are increased by a predetermined scaling factor, and all voltages are reduced by the same scaling factor, leading to a reduction of the junction depletion width. As a result, the subthreshold current would be expected to remain essentially the same for the long channel device and the scaled down device. However, there are limitations to the amount of scaling that can be accomplished and, as such, reduction in the channel length with respect to buried channel devices still results in limitations with respect to leakage. In order to further reduce the channel length of the buried-channel transistor, other techniques in addition to scaling will be required.
The present application discloses an innovative circuit device architecture, an innovative transistor structure, and an innovative method for forming a buried channel transistor.
The disclosed innovative integrated circuit structure is a CMOS integrated circuit, in which the PMOS devices each include a buried channel region. The P+ source/drain regions are separated from the channel region by N-type lateral field isolating regions. Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the corners of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal.
The disclosed innovative transistor is a P-channel insulated-gate field-effect transistor which includes N-type lateral field isolating regions interposed between the channel and the P+ source/drain regions. Thus, the lateral field isolating regions are closely coupled to the enhanced electric field at the corners of the gate.
The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant. Both of these implanting steps are preferably performed after the polysilicon gate layer is encapsulated (by a thin oxide layer), but before the sidewall oxide spacers (which will define a lateral separation between the gate level and the source/drain implant locations) are formed.
Many prior VLSI CMOS processes have specified a minimum length, for the P-channel devices, which is slightly longer than the minimum length for the N-channel devices (e.g. 0.2 micron longer). The present invention avoids the need for this disparity in sizes.
Another way to use the advantages of the present invention is simply to save about 0.2 micron of channel length, for geometries near 1 micron. This is a substantial saving. Moreover, a decrease in minimum channel length confers several other advantages: for a given device width, the drive capability of the device is increased, and the on-state series resistance is decreased. The switching speed of logic circuits is also likely to be increased.
A further advantage of the disclosed innovative teachings is that the present invention helps to avoid back-conduction through the channel. That is, one of the adverse conditions which integrated circuits commonly encounter is voltages on an external pin which exceed the supply voltage V.sub.DD. (Such voltages can occur, for example, due to electrical noise picked up by a signal line.) When such an overshoot voltage becomes more than a diode drop above the supply voltage V.sub.DD, junctions in the substrate will (undesirably) begin to conduct current, and carriers will be injected into the substrate. Such injected carriers can discharge capacitive nodes and/or cause logic gates to switch, so that the chip must be reset. This is undesirable. In practice, this will often occur at voltages which are less than one diode drop above V.sub.DD.
It has been discovered that such low-voltage upset may be caused by backwards conduction through a PMOS transistor connected to the incoming line. That is, in a typical CMOS output driver configuration, one of the transistor's two P+ diffusions (which would normally act as the PMOS transistor's drain) is connected to the external line, and the other is connected to the power supply V.sub.DD. The N-well is also typically connected to V.sub.DD. Now, suppose that the gate voltage happens to be at approximately V.sub.DD -V.sub.TP. In this case, when the P+ drain diffusion is pulled above V.sub.DD, this may turn on the transistor, with a direction of flow which is opposite to its normal direction of current flow. This backwards conduction may undesirably pull up the potential of other nodes in the chip.
It has been experimentally discovered that the present invention provides added an margin of protection against such V.sub.DD overshoot on I/O lines. Thus, integrated circuits which include PMOS transistor structures as disclosed and claimed herein are better able to withstand applied voltages in excess of V.sub.DD, without reverse-buried-channel leakage to the source.
A further innovative teaching disclosed herein is that the peak doping concentration of the lateral field isolating regions are preferably formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal.
This retrograde profile of the lateral field isolating regions has the further advantage that gate-induced inversion of these regions can easily occur near their upper boundary (so that the device threshold voltage is not increased), while the more heavily doped lower portions of these regions help to minimize the width of the depletion regions extending from the gate.
It should be noted that the operation of the lateral field isolating regions is, in some ways, exactly opposite to that of the lightly-doped drain extension regions (LDD regions) commonly used in VLSI processing. LDD regions reduce hot carrier generation, by reducing the peak electric field magnitude, by increasing the width of the depletion region at the drain boundary. By contrast, the lateral field isolating regions provided by the innovative teachings herein decrease the width of the depletion region at the drain boundary, which necessarily means that the peak electric field magnitude at the drain boundary will be increased. However, hot carrier generation is much more a problem in NMOS devices than in the PMOS devices, and the present invention recognizes that advantages can be obtained by going contrary to the conventional teachings, in the PMOS devices only.
A further innovative teaching disclosed herein is an advantageous combination of steps in a CMOS process. The preferred process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. Preferably the lateral field isolating regions are formed at a point in the process flow which is close to the time when LDD regions are formed on the NMOS devices: Preferably both are formed after the polysilicon gate layer is encapsulated (by a thin oxide layer), but before the sidewall oxide spacers (which will define a lateral separation between the gate level and the source/drain implant locations) are formed.